Thiết kế VLSI - Bài 2 (HUST) Thầy Nguyễn Vũ Thắng

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goupee.vn goupee.com Design and Implementation of VLSI Systems Lecture02 CMOS logic cuu duong than cong . com fb.com/goupee.vn CuuDuongThanCong.com https://fb.com/tailieudientucntt

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goupee.vnImpact of doping on silicon resistivity goupee.com silicon 4.9951022 atoms in cm3 Resistivity 3.2  105 Ωcm dope with phosphorous dope with or arsenic  boron  n-type p-type 1 atom in billion  cuu duong than cong . com1 atom in billion  1 atom in million  1 atom in million  1 atom in thousand  1 atom in thousand   Electrons are more mobile/faster than holes fb.com/goupee.vn CuuDuongThanCong.com https://fb.com/tailieudientucntt

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goupee.vnWhat happens if we sandwich p & n types?goupee.com A Al p n B One-dimensional representation cuu duong than cong . com ➢Inequilibrium,thedriftanddiffusioncomponents ofcurrent arebalanced;thereforethenetcurrentflow ingacross the junctionis zero. fb.com/goupee.vn CuuDuongThanCong.com https://fb.com/tailieudientucntt

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goupee.vnPN-junction regions of operation goupee.com A forward bias In reverse bias, the width decreases the potential of the depletion region drop across the increases. The diode actscuu duong than cong . comjunction. As a result, as voltage-controlled the magnitude of the electric field decreases capacitor. and the width of the depletion region fb.com/goupee.vn narrows. CuuDuongThanCong.com https://fb.com/tailieudientucntt

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goupee.vnnMOS and pMOS transistors goupee.com Each transistor consists of a stack of a conducting gate, an insulating layer of silicon dioxide and a semiconductor substrate (body or bulk) nMOS transistor pMOS transistor Source Gate Drain Source Gate Drain Polysilicon Polysilicon SiO2 SiO2 polysilicon gate W p+ p+ n+ n+ t ox p bulk Si L SiO gate oxide n bulk Si n+ n+ 2 (good insulator,  = 3.9) ox p-type body cuu duong than cong . com Body is typically grounded Body is typically at supply voltage fb.com/goupee.vn CuuDuongThanCong.com https://fb.com/tailieudientucntt

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goupee.vnnMOS transistor goupee.com Source Gate Drain Polysilicon SiO2 n+ n+ p bulk Si g=0: When the gate is at a low voltage (VGS < VTN): ➢ p-type body is at low voltage ➢ source and drain-junctions diodes are OFF ➢ transistor is OFF, no current flows g=1: When the gate is at a high voltage (VGS ≥ VTN): ➢ negative charge attracted to bodycuu duong than cong . com ➢ inverts a channel under gate to n-type ➢ transistor ON, current flows, transistor can be viewed as a resistor fb.com/goupee.vn CuuDuongThanCong.com https://fb.com/tailieudientucntt

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goupee.vnnMOS pass ‘0’ more strongly than ‘1’ goupee.com Source Gate Drain Polysilicon SiO2 n+ n+ p bulk Si • Why does ‘1’ pass degraded?cuu duong than cong . com fb.com/goupee.vn CuuDuongThanCong.com https://fb.com/tailieudientucntt

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goupee.vnpMOS transistor goupee.com Source Gate Drain Polysilicon SiO2 p+ p+ n bulk Si g=0: When the gate is at a low voltage (VGS < VTP): ➢ positive charge attracted to body ➢ inverts a channel under gate to p-type ➢ transistor ON, current flows g=1: When the gate is at a high voltage (VGS ≥ VTP): ➢ negative charge attracted to bodycuu duong than cong . com ➢ source and drain junctions are OFF ➢ transistor OFF, no current flows fb.com/goupee.vn CuuDuongThanCong.com https://fb.com/tailieudientucntt

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goupee.vnpMOS pass ‘1’ more strongly than ‘0’ goupee.com Source Gate Drain Polysilicon SiO2 p+ p+ n bulk Si cuu duong than cong . com • Why does ‘0’ pass degraded? fb.com/goupee.vn CuuDuongThanCong.com https://fb.com/tailieudientucntt

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goupee.vnAn nMOS and pMOS make up an invertergoupee.com cuu duong than cong . compMOS + nMOS = CMOS fb.com/goupee.vn CuuDuongThanCong.com https://fb.com/tailieudientucntt

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goupee.vnMore CMOS gates goupee.com B A B F = AB 0 What is this gate function? What’s wrong about this design? cuu duong than cong . com fb.com/goupee.vn CuuDuongThanCong.com https://fb.com/tailieudientucntt

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goupee.vn3-input NANDs goupee.com cuu duong than cong . com If: Pull up network = 1 => pull down network must = 0 If: Pull up network = 0 => pull down network must = 1 fb.com/goupee.vn CuuDuongThanCong.com https://fb.com/tailieudientucntt

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goupee.vn3-input NANDs goupee.com What are the advantages of CMOS circuit style? cuu duong than cong . com fb.com/goupee.vn CuuDuongThanCong.com https://fb.com/tailieudientucntt

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goupee.vnSeries-Parallel Combinations goupee.com cuu duong than cong . com fb.com/goupee.vn CuuDuongThanCong.com https://fb.com/tailieudientucntt

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goupee.vnWhat are the transistor schematics of the goupee.com NOR gate? cuu duong than cong . com fb.com/goupee.vn CuuDuongThanCong.com https://fb.com/tailieudientucntt

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goupee.vnAnd-Or-Inverter (AOI) gate goupee.com cuu duong than cong . com fb.com/goupee.vn CuuDuongThanCong.com https://fb.com/tailieudientucntt

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goupee.vnCMOS gate design steps goupee.com Steps: -Design pull down network -Use the inverse of the given function -NMOS circuit -Design pull up network -Use the opposite network of the pull down network: parallel - serial; serial – parallel -PMOS circuit -Combine 2 networkscuu duong than cong . com fb.com/goupee.vn CuuDuongThanCong.com https://fb.com/tailieudientucntt

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goupee.vnExamples goupee.com Example 1.2 Sketch a static CMOS gate computing Y = (A + B + C) · D cuu duong than cong . com fb.com/goupee.vn CuuDuongThanCong.com https://fb.com/tailieudientucntt

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goupee.vnTransmission gate goupee.com cuu duong than cong . com fb.com/goupee.vn CuuDuongThanCong.com https://fb.com/tailieudientucntt

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goupee.vnTri-state inverter goupee.com cuu duong than cong . com fb.com/goupee.vn CuuDuongThanCong.com https://fb.com/tailieudientucntt

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