ng .c om Design and Implementation of VLSI Systems Lecture05 cu u du on g th an co Delay om Delay cu u du on g th an co ng .c Introduction Delay Estimation Logical Effort for Delay Estimation om Introduction th an co ng .c Critical paths are those which require attention to timing details Timing analyzer is a design tool that automatically finds the slowest path in a logic design du on g Altera: Classic Timing Analyzer, TimeQuest Timing Analyzer Synopsys: PrimeTime The critical paths can be affected at four main levels cu u The architecture/ micro-architecture level The logic level The circuit level The layout level Delay definitions om tpdr: rising propagation delay .c Max time: From input to rising output crossing VDD/2 ng tpdf: falling propagation delay co Max time: From input to falling output crossing VDD/2 th an tpd: average propagation delay. tpd = (tpdr + tpdf)/2 tcdr: rising contamination (best-case) delay du on g Min time: From input to rising output crossing VDD/2 tcdf: falling contamination (best-case) delay Min time: From input to falling output crossing VDD/2 cu u tcd: average contamination delay. tcd = (tcdr + tcdf)/2 tr: rise time - from output crossing 0.2 VDD to 0.8 VDD tf: fall time - from output crossing 0.8 VDD to 0.2 VDD cu u du on g th an co ng .c om Delay definitions Delay definitions om cu u du on g th an co ng .c Driver: gate

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