Kiến trúc máy tính - MIPS Green Sheet (HUST)

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Next by this authorSlide Kỹ thuật ghép nối máy tính (Chương 6) - HUST. GV. Bùi Quốc Anh Previous in courseSlide Kiến trúc máy tính - GV. Nguyễn Kim Khánh (HUST)

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Tài liệu tham khảo nhanh (Green Sheet) về tập lệnh MIPS, bao gồm các lệnh số học, lệnh dấu phẩy động, định dạng lệnh, và quy ước đặt tên thanh ghi. Đây là tài liệu hỗ trợ học tập về kiến trúc bộ xử lý MIPS.

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Document name: Kiến trúc máy tính - MIPS Green Sheet (HUST)
School / Course: Đại học Bách khoa Hà Nội · Kiến trúc máy tính
Content: Đây là tài liệu tham khảo nhanh về tập lệnh MIPS, bao gồm các lệnh cốt lõi, định dạng lệnh và thông tin thanh ghi. Nó được thiết kế để hỗ trợ việc học và thực hành kiến trúc máy tính.
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Page 1

M I P S 1 ARITHMETIC CORE INSTRUCTION SET 2 OPCODE / FMT /FT Reference Data FOR- / FUNCT NAME, MNEMONIC MAT OPERATION (Hex) CORE INSTRUCTION SET OPCODE Branch On FP True bc1t FI if(FPcond)PC=PC+4+BranchAddr (4) 11/8/1/-- FOR- / FUNCT Branch On FP False bc1f FI if(!FPcond)PC=PC+4+BranchAddr(4) 11/8/0/-- NAME, MNEMONIC MAT OPERATION (in Verilog) (Hex) Divide div R Lo=R[rs]/R[rt]; Hi=R[rs]%R[rt] 0/--/--/1a Add add R R[rd] = R[rs] + R[rt] (1) 0 / 20 Divide Unsigned divu R Lo=R[rs]/R[rt]; Hi=R[rs]%R[rt] (6) 0/--/--/1b hex FP Add Single FR F[fd ]= F[fs] + F[ft] 11/10/--/0 add.s Add Immediate addi I R[rt] = R[rs] + SignExtImm (1,2) 8hex FP Add {F[fd],F[fd+1]} = {F[fs],F[fs+1]} + Add Imm. Unsigned I R[rt] = R[rs] + SignExtImm (2) 9 Double add.d FR 11/11/--/0 addiu hex {F[ft],F[ft+1]} Add Unsigned addu R R[rd] = R[rs] + R[rt] 0 / 21 FP Compare Single c.x.s* FR FPcond = (F[fs] op F[ft]) ? 1 : 0 11/10/--/y hex 0 / 24 FP Compare FR FPcond = ({F[fs],F[fs+1]} op 11/11/--/y And and R R[rd] = R[rs] & R[rt] hex Double c.x.d* {F[ft],F[ft+1]}) ? 1 : 0 And Immediate andi I R[rt] = R[rs] & ZeroExtImm (3) chex * (x is eq, lt, or le) (op is ==, <, or <=) ( y is 32, 3c, or 3e) if(R[rs]==R[rt]) FP Divide Single div.s FR F[fd] = F[fs] / F[ft] 11/10/--/3 Branch On Equal beq I 4hex FP Divide {F[fd],F[fd+1]} = {F[fs],F[fs+1]} / PC=PC+4+BranchAddr (4) div.d FR 11/11/--/3 if(R[rs]!=R[rt]) Double {F[ft],F[ft+1]} Branch On Not Equalbne I 5hex FP Multiply Single mul.s FR F[fd] = F[fs] * F[ft] 11/10/--/2 PC=PC+4+BranchAddr (4) Jump J PC=JumpAddr (5) 2 FP Multiply FR {F[fd],F[fd+1]} = {F[fs],F[fs+1]} * 11/11/--/2 j hex Double mul.d {F[ft],F[ft+1]} Jump And Link jal J R[31]=PC+8;PC=JumpAddr (5) 3hex FP Subtract Single sub.s FR F[fd]=F[fs] - F[ft] 11/10/--/1 Jump Register jr R PC=R[rs] 0 / 08hex FP Subtract FR {F[fd],F[fd+1]} = {F[fs],F[fs+1]} - 11/11/--/1 2. Fold bottom side (columns 3 and 4) together Double sub.d {F[ft],F[ft+1]} Load Byte Unsigned I R[rt]={24’b0,M[R[rs] 24 lbu +SignExtImm](7:0)} (2) hex Load FP Single lwc1 I F[rt]=M[R[rs]+SignExtImm] (2) 31/--/--/-- Load Halfword R[rt]={16’b0,M[R[rs] Load FP I F[rt]=M[R[rs]+SignExtImm]; (2) 35/--/--/-- lhu I 25 Double ldc1 F[rt+1]=M[R[rs]+SignExtImm+4] Unsigned +SignExtImm](15:0)} (2) hex 30 Move From Hi mfhi R R[rd] = Hi 0 /--/--/10 Load Linked ll I R[rt] = M[R[rs]+SignExtImm] (2,7) hex Move From Lo R R[rd] = Lo 0 /--/--/12 mflo Load Upper Imm. lui I R[rt] = {imm, 16’b0} fhex Move From Control mfc0 R R[rd] = CR[rs] 10 /0/--/0 Load Word lw I R[rt] = M[R[rs]+SignExtImm] (2) 23hex Multiply mult R {Hi,Lo} = R[rs] * R[rt] 0/--/--/18 Nor nor R R[rd] = ~ (R[rs] | R[rt]) 0 / 27 Multiply Unsigned multu R {Hi,Lo} = R[rs] * R[rt] (6) 0/--/--/19 hex Shift Right Arith. R R[rd] = R[rt] >>> shamt 0/--/--/3 sra Or or R R[rd] = R[rs] | R[rt] 0 / 25hex Store FP Single I M[R[rs]+SignExtImm] = F[rt] (2) 39/--/--/-- swc1 Or Immediate ori I R[rt] = R[rs] | ZeroExtImm (3) dhex Store FP M[R[rs]+SignExtImm] = F[rt]; (2) Double sdc1 I 3d/--/--/-- Set Less Than slt R R[rd] = (R[rs] < R[rt]) ? 1 : 0 0 / 2a M[R[rs]+SignExtImm+4] = F[rt+1] hex Set Less Than Imm. slti I R[rt] = (R[rs] < SignExtImm)? 1 : 0 (2) ahex FLOATING-POINT INSTRUCTION FORMATS Set Less Than Imm. I R[rt] = (R[rs] < SignExtImm) b FR opcode fmt ft fs fd funct Unsigned sltiu ? 1 : 0 (2,6) hex 31 26 25 21 20 16 15 11 10 6 5 0 Set Less Than Unsig. sltu R R[rd] = (R[rs] < R[rt]) ? 1 : 0 (6) 0 / 2bhex FI opcode fmt ft immediate Shift Left Logical sll R R[rd] = R[rt] << shamt 0 / 00hex 31 26 25 21 20 16 15 0 Shift Right Logical srl R R[rd] = R[rt] >> shamt 0 / 02hex PSEUDOINSTRUCTION SET 1. Pull along perforation to separate cardM[R[rs]+SignExtImm](7:0) = NAME MNEMONIC OPERATION Store Byte sb I 28hex R[rt](7:0) (2) Branch Less Than blt if(R[rs]<R[rt]) PC = Label M[R[rs]+SignExtImm] = R[rt]; Branch Greater Than bgt if(R[rs]>R[rt]) PC = Label Store Conditional sc I 38hex Branch Less Than or Equal ble if(R[rs]<=R[rt]) PC = Label R[rt] = (atomic) ? 1 : 0 (2,7) M[R[rs]+SignExtImm](15:0) = Branch Greater Than or Equal bge if(R[rs]>=R[rt]) PC = Label Store Halfword sh I 29hex Load Immediate li R[rd] = immediate R[rt](15:0) (2) Move move R[rd] = R[rs] Store Word sw I M[R[rs]+SignExtImm] = R[rt] (2) 2bhex Subtract R R[rd] = R[rs] - R[rt] (1) 0 / 22 REGISTER NAME, NUMBER, USE, CALL CONVENTION sub hex NAME NUMBER USE PRESERVEDACROSS Subtract Unsigned subu R R[rd] = R[rs] - R[rt] 0 / 23hex A CALL? (1) May cause overflow exception $zero 0 The Constant Value 0 N.A. (2) SignExtImm = { 16{immediate[15]}, immediate } $at 1 Assembler Temporary No (3) ZeroExtImm = { 16{1b’0}, immediate } Values for Function Results (4) BranchAddr = { 14{immediate[15]}, immediate, 2’b0 } $v0-$v1 2-3 and Expression Evaluation No (5) JumpAddr = { PC+4[31:28], address, 2’b0 } (6) Operands considered unsigned numbers (vs. 2 s comp.)’ $a0-$a3 4-7 Arguments No (7) Atomic test&set pair; R[rt] = 1 if pair atomic, 0 if not atomic $t0-$t7 8-15 Temporaries No BASIC INSTRUCTION FORMATS $s0-$s7 16-23 Saved Temporaries Yes $t8-$t9 24-25 Temporaries No R opcode rs rt rd shamt funct $k0-$k1 26-27 Reserved for OS Kernel No 31 26 25 21 20 16 15 11 10 6 5 0 $gp 28 Global Pointer Yes I opcode rs rt immediate $sp 29 Stack Pointer Yes 31 26 25 21 20 16 15 0 $fp 30 Frame Pointer Yes J opcode address $ra 31 Return Address Yes MIPS Reference Data Card (“Green Card”)31 26 25 0 Copyright 2009 by Elsevier, Inc., All rights reserved. From Patterson and Hennessy, Computer Organization and Design, 4th ed. goupee.com fb.com/groups/goupee

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3 IEEE 754 FLOATING-POINT 4 OPCODES, BASE CONVERSION, ASCII SYMBOLS STANDARD IEEE 754 Symbols MIPS (1) MIPS (2) MIPS Deci- Hexa- ASCII Deci- Hexa- ASCII Exponent Fraction Object opcode funct funct Binary mal deci- Char- mal deci- Char- (-1)S × (1 + Fraction) × 2(Exponent - Bias) 0 0 ± 0 (31:26) (5:0) (5:0) mal acter mal acter 0 ≠0 ± Denorm (1) sll add.f 00 0000 0 0 NUL 64 40 @ where Single Precision Bias = 127, sub.f 00 0001 1 1 SOH 65 41 A Double Precision Bias = 1023. 1 to MAX - 1 anything ± Fl. Pt. Num. j srl mul.f 00 0010 2 2 STX 66 42 B MAX 0 ±∞ jal sra div.f 00 0011 3 3 ETX 67 43 C IEEE Single Precision and MAX ≠0 NaN beq sllv sqrt.f 00 0100 4 4 EOT 68 44 D Double Precision Formats: S.P. MAX = 255, D.P. MAX = 2047 bne abs.f 00 0101 5 5 ENQ 69 45 E blez srlv mov.f 00 0110 6 6 ACK 70 46 F S Exponent Fraction bgtz srav neg.f 00 0111 7 7 BEL 71 47 G 31 30 23 22 0 addi jr 00 1000 8 8 BS 72 48 H S Exponent Fraction addiu jalr 00 1001 9 9 HT 73 49 I slti movz 00 1010 10 a LF 74 4a J 63 62 52 51 0 sltiu movn 00 1011 11 b VT 75 4b K MEMORY ALLOCATION STACK FRAME andi syscall round.w.f 00 1100 12 c FF 76 4c L Stack ... Higher ori break trunc.w.f 00 1101 13 d CR 77 4d M $sp 7fff fffchex Memory Argument 6 Addresses xori ceil.w.f 00 1110 14 e SO 78 4e N Argument 5 lui sync floor.w.f 00 1111 15 f SI 79 4f O $fp mfhi 01 0000 16 10 DLE 80 50 P Saved Registers (2) mthi 01 0001 17 11 DC1 81 51 Q Dynamic Data Stack mflo movz.f 01 0010 18 12 DC2 82 52 R $gp 1000 8000 Grows .f 01 0011 19 13 DC3 83 53 S hex mtlo movn Static Data 01 0100 20 14 DC4 84 54 T 1000 0000 Local Variables 2. Fold bottom side (columns 3 and 4) together 01 0101 21 15 NAK 85 55 U hex $sp 01 0110 22 16 SYN 86 56 V Text Lower 01 0111 23 17 ETB 87 57 W pc 0040 0000hex Memory mult 01 1000 24 18 CAN 88 58 X Addresses multu 01 1001 25 19 EM 89 59 Y 0 Reserved hex div 01 1010 26 1a SUB 90 5a Z divu 01 1011 27 1b ESC 91 5b [ DATA ALIGNMENT 01 1100 28 1c FS 92 5c \ Double Word 01 1101 29 1d GS 93 5d ] 01 1110 30 1e RS 94 5e ^ Word Word 01 1111 31 1f US 95 5f _ Halfword Halfword Halfword Halfword lb add cvt.s.f 10 0000 32 20 Space 96 60 ‘ lh addu cvt.d.f 10 0001 33 21 ! 97 61 a Byte Byte Byte Byte Byte Byte Byte Byte lwl sub 10 0010 34 22 " 98 62 b 0 1 2 3 4 5 6 7 lw subu 10 0011 35 23 # 99 63 c Value of three least significant bits of byte address (Big Endian) lbu and cvt.w.f 10 0100 36 24 $ 100 64 d EXCEPTION CONTROL REGISTERS: CAUSE AND STATUS lhu or 10 0101 37 25 % 101 65 e B Interrupt Exception lwr xor 10 0110 38 26 & 102 66 f nor 10 0111 39 27 ’ 103 67 g D Mask Code sb 10 1000 40 28 ( 104 68 h 31 15 8 6 2 sh 10 1001 41 29 ) 105 69 i Pending U E I swl slt 10 1010 42 2a * 106 6a j Interrupt M L E sw sltu 10 1011 43 2b + 107 6b k 15 8 4 1 0 1. Pull along perforation to separate card 10 1100 44 2c , 108 6c l BD = Branch Delay, UM = User Mode, EL = Exception Level, IE =Interrupt Enable 10 1101 45 2d - 109 6d m EXCEPTION CODES swr 10 1110 46 2e . 110 6e n cache 10 1111 47 2f / 111 6f o Number Name Cause of Exception Number Name Cause of Exception ll tge c.f.f 11 0000 48 30 0 112 70 p 0 Int Interrupt (hardware) 9 Bp Breakpoint Exception lwc1 tgeu c.un.f 11 0001 49 31 1 113 71 q 4 AdEL Address Error Exception 10 RI Reserved Instruction lwc2 tlt c.eq.f 11 0010 50 32 2 114 72 r (load or instruction fetch) Exception pref tltu c.ueq.f 11 0011 51 33 3 115 73 s 5 AdES Address Error Exception 11 CpU Coprocessor teq c.olt.f 11 0100 52 34 4 116 74 t (store) Unimplemented ldc1 c.ult.f 11 0101 53 35 5 117 75 u Bus Error on Arithmetic Overflow ldc2 tne c.ole.f 11 0110 54 36 6 118 76 v 6 IBE Instruction Fetch 12 Ov Exception c.ule.f 11 0111 55 37 7 119 77 w Bus Error on sc c.sf.f 11 1000 56 38 8 120 78 x 7 DBE Load or Store 13 Tr Trap swc1 c.ngle.f 11 1001 57 39 9 121 79 y 8 Sys Syscall Exception 15 FPE Floating Point Exception swc2 c.seq.f 11 1010 58 3a : 122 7a z c.ngl.f 11 1011 59 3b ; 123 7b { SIZE PREFIXES (10x for Disk, Communication; 2x for Memory) c.lt.f 11 1100 60 3c < 124 7c | PRE- PRE- PRE- PRE- sdc1 c.nge.f 11 1101 61 3d = 125 7d } sdc2 c.le.f 11 1110 62 3e > 126 7e ~ SIZE FIX SIZE FIX SIZE FIX SIZE FIX c.ngt.f 11 1111 63 3f ? 127 7f DEL 103, 210 Kilo- 1015, 250 Peta- 10-3 milli- 10-15 femto- (1) opcode(31:26) == 0 106, 220 Mega- 1018, 260 Exa- 10-6 micro- 10-18 atto- (2) opcode(31:26) == 17ten (11hex); if fmt(25:21)==16ten (10hex) f = s (single); 109, 230 Giga- 1021, 270 Zetta- 10-9 nano- 10-21 zepto- if fmt(25:21)==17ten (11hex) f = d (double) 1012, 240 Tera- 1024, 280 Yotta- 10-12 pico- 10-24 yocto- The symbol for each prefix is just its first letter, except μ is used for micro. Copyright 2009 by Elsevier, Inc., All rights reserved. From Patterson and Hennessy, Computer Organization and Design, 4th ed. MIPS Reference Data Card (“Green Card”) goupee.com fb.com/groups/goupee

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MIPS Reference Data Card (“Green Card”) 1. Pull along perforation to separate card 2. Fold bottom side (columns 3 and 4) together ARITHMETIC CORE INSTRUCTION SET 1 M I P S Reference Data CORE INSTRUCTION SET FORNAME, MNEMONIC MAT OPERATION (in Verilog) add Add R R[rd] = R[rs] + R[rt] OPCODE / FUNCT (Hex) (1) 0 / 20hex addi I R[rt] = R[rs] + SignExtImm (1,2) Add Imm. Unsigned addiu I R[rt] = R[rs] + SignExtImm (2) Add Immediate Add Unsigned addu R R[rd] = R[rs] + R[rt] And and R R[rd] = R[rs] & R[rt] And Immediate andi I Branch On Equal beq I Branch On Not Equal bne I 0 / 24hex Jump j J Jump And Link jal J R[31]=PC+8;PC=JumpAddr Jump Register jr ll R PC=R[rs] R[rt]={24’b0,M[R[rs] I +SignExtImm](7:0)} R[rt]={16’b0,M[R[rs] I +SignExtImm](15:0)} I R[rt] = M[R[rs]+SignExtImm] Load Upper Imm. lui I R[rt] = {imm, 16’b0} Load Word lw I R[rt] = M[R[rs]+SignExtImm] Nor nor R R[rd] = ~ (R[rs] | R[rt]) Or or R R[rd] = R[rs] | R[rt] Or Immediate ori I Set Less Than slt R R[rd] = (R[rs] < R[rt]) ? 1 : 0 Load Halfword Unsigned Load Linked lhu 9hex 0 / 21hex R[rt] = R[rs] & ZeroExtImm if(R[rs]==R[rt]) PC=PC+4+BranchAddr if(R[rs]!=R[rt]) PC=PC+4+BranchAddr PC=JumpAddr Load Byte Unsigned lbu 8hex (3) chex (4) 4hex (4) (5) (5) 5hex 2hex 3hex 0 / 08hex (2) (2) (2,7) 24hex 25hex 30hex fhex (2) 23hex 0 / 27hex 0 / 25hex R[rt] = R[rs] | ZeroExtImm (3) dhex 0 / 2ahex Shift Left Logical sll Shift Right Logical srl R[rt] = (R[rs] < SignExtImm)? 1 : 0 (2) ahex R[rt] = (R[rs] < SignExtImm) bhex I ?1:0 (2,6) R R[rd] = (R[rs] < R[rt]) ? 1 : 0 (6) 0 / 2bhex 0 / 00hex R R[rd] = R[rt] << shamt 0 / 02hex R R[rd] = R[rt] >> shamt Store Byte sb I Store Conditional sc I Store Halfword sh I Store Word sw I Subtract sub R R[rd] = R[rs] - R[rt] Subtract Unsigned subu Set Less Than Imm. slti Set Less Than Imm. sltiu Unsigned Set Less Than Unsig. sltu FLOATING-POINT INSTRUCTION FORMATS I M[R[rs]+SignExtIm

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